The error correction code, known as ECC, self-detects and retrieves errors in data transfer, now embedded in the chip, said Kim Dong-kyun, research fellow for DRAM design at SK hynix, the world’s second-largest memory chipmaker. Such error-checking protocol is crucial in the future of automotive memory that transfers and processes vast amount of data inside the brain of a self-driving car.
|Kim Dong-kyun, research fellow for DRAM design at SK hynix, speaks during an interview with The Korea Herald at the company’s headquarters in Icheon, Gyeonggi Province, Jan. 16. (SK hynix)|
“Because quality is the most important issue in automobiles, it is imperative that automotive memory chips have the ECC,” Kim said in an interview with The Korea Herald. “The ECC technology has been adopted by our company’s DDR5 that will be more reliable for the growing automotive memory market.”
Technological specifications for the ECC had not been defined by international standards until before SK hynix announced the world’s first JEDEC standards-based DDR5 in November. It is widely expected to meet demand from sectors with intensive computing needs, such as big data analytics and artificial intelligence.
A 16-gigabit DDR5 DRAM supports a data transfer rate of 5.2 gigabits per second, about 60 percent faster than the previous generation, which can process 41.6 gigabytes of data --11 full-high definition video files (3.7 GB each) -- per second.
According to market researcher IDC, demand for DDR5 is expected to rise from 2020, accounting for 25 percent of the total DRAM market in 2021 and 44 percent in 2022.
Kim has spent 24 years designing DRAMs that have evolved through five generations, and the latest DDR5 is a source of pride for him.
“Many say we have reached a limitation in nanometer technology, but we have done this again, which we ourselves had thought was impossible,” Kim said.
SK hynix spent around two years on research and development of new technologies for DDR5, he said.
“We concentrated R&D efforts on developing a set of element technologies that enable raising the speed while maintaining the operating voltage and removing noise during a high-speed transmission,” the research fellow explained.
“We have developed a multi-phase synchronization technology that enables keeping the voltage during a high-speed operation in a chip at a low level by placing multiple phases within the IP circuit, so the power used on each phase is low but the speed is high when combined.”
The current speed of DDR5 is 5.2 gigabits per second, and the company is further raising it to 6.4 gigabits per second by 2022.
Kim already has a plan for the sixth generation of DRAM, which is forecast to be developed in five or six years.
“We are discussing several concepts of the post DDR5,” he said. “One concept is to maintain the current trend of speeding up the data transmission, and another is to combine the DRAM technology with system-on-chip process technologies, such as CPU.”
By Song Su-hyun (firstname.lastname@example.org)